module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
);

    always @(posedge clk) begin
        if(reset) begin
           	c_d <= 4'd1;
        end
        else begin
            if(Q == 4'd11) begin
               	c_d <= 4'd1;
            end
        end
    end
    
    assign c_load = reset || ((Q == 4'd12) && enable);
    assign c_enable = enable;
    
    count4 u_count4_0(
        .clk(clk),
        .enable(c_enable),
        .load(c_load),
        .d(c_d),
        .Q(Q)
    );

endmodule
